1. Field of the Invention
The present invention relates to a computer readable storage medium having a logic synthesis program, and a logic synthesis method and a logic synthesis apparatus, for generating information about the constitution of desired logic circuitry, which is comprised of a plurality of pieces of cell information, based on specifications of the desired circuitry. More particularly, it relates to a computer readable storage medium having a logic synthesis program, and a logic synthesis method and a logic synthesis apparatus, capable of constituting desired logic circuitry using a tristate bus based on specifications of the desired circuitry.
2. Description of the Prior Art
Japanese Patent Application Publication (KOKAI) No. 3-182969, No. 6-251104, and No. 10-187787 disclose a prior art logic synthesis apparatus for generating information about the constitution of a desired circuit, which consists of a plurality of pieces of cell information, based on specifications of the desired circuit written in a hardware description language. Referring now to FIG. 12, there is illustrated a block diagram showing the structure of such a prior art logic synthesis apparatus. In the figure, reference numeral 1 denotes a central processing unit for performing a logic synthesis function, 2 denotes a memory for storing information required for the logic synthesis function and so on, 3 denotes an input unit, 4 denotes a display unit, 5 denotes an input/output (I/O) port, and 6 denotes a system bus. Further, reference numeral 7 denotes a cell library, 8 denotes specification information about specifications of desired circuitry on which the logic synthesis function is to be performed, written in a hardware description language or HDL, and 54 denotes information provided as timing limitations imposed on the desired circuitry on which the logic synthesis function is to be performed, i.e. information about timing of a clock signal to be applied to flip-flops and latches included in the circuitry.
In operation, the central processing unit 1 performs a logic analysis based on the specification information 8 read out of the memory 2 and then generates standard circuit information about the constitution of the desired circuitry. The central processing unit 1 then modifies the standard circuit information so that the standard circuit information satisfies the timing information 54 about the timing of the clock signal, which is read out of the memory 2, to generate modified circuit information that complies with the timing information. For example, the central processing unit 1 adjusts the driving capability of each of a plurality of components such as flip-flops, latches, and logic gates so that data transfer among them is completed in one clock cycle so as to generate modified circuit information, and then stores it in the memory 2.
A problem with such a prior art logic synthesis apparatus is that the mutual timing of signals applied to components that transmit and receive data using a tristate bus cannot be optimized because the timing limitations mainly include information about the timing of a clock signal applied to storage elements such as flip-flops and latches and therefore a control signal applied to a tristate buffer is assumed to be a kind of data signal. This can result in a undesired configuration of the target circuitry in which a unidirectional bus is provided for each of cells and sequential circuits that receives signals via the unidirectional bus and a selector is provided for each unidirectional bus in order for each cell or sequential circuit to furnish a signal via each unidirectional bus even though the circuitry can be constituted using a tristate bus that also serves as a bidirectional bus. As a result, the circuitry designed can have a number of unnecessary unidirectional buses, thus increasing in complexity and size.
The present invention is made to overcome the above problem. It is therefore an object of the present invention to provide a computer readable storage medium having a logic synthesis program, and a logic synthesis method and a logic synthesis apparatus, capable of optimizing the mutual timing of signals applied to components that transmit and receive data using a tristate bus, thus constituting desired circuitry using the tristate bus.
In accordance with one aspect of the present invention, there is provided a computer readable storage medium having a logic synthesis code embodied therein, the logic synthesis code comprising: a standard design function for causing a computer to generate standard circuit information about target circuitry on which a logic synthesis function is to be performed, based on specifications of the target circuitry written in a hardware description language, the standard circuit information logically matching the specifications; a timing design function for causing the computer to generate modified circuit information by modifying the standard circuit information so that the standard circuit information satisfies both an ideal clock signal condition defining an ideal clock signal to be applied to one or more sequential circuits included in the target circuitry, and at least either of a first ideal assertion period condition defining an ideal period of time during which each of one or more tristate buffers included in the target circuitry is asserted and a second ideal assertion period condition defining an ideal period of time during which each of one or more other sequential circuits for latching an output of a tristate buffer, which are included in the target circuitry is asserted; and an output function for outputting the modified circuit information from the timing design function.
In this specification, a sequential circuit is referred to as a circuit including either a flip-flop or a latch.
In accordance with a preferred embodiment of the present invention, the timing design function divides the standard circuit information into a plurality of pieces of standard circuit block information that are associated with a plurality of standard circuit blocks, respectively, while defining as boundaries one or more sequential circuits on which the ideal clock signal condition is imposed, and at least either of one or more tristate buffers on each of which the first ideal assertion period condition is imposed and one or more other sequential circuits on each of which the second ideal assertion period condition is imposed, and then modifies each of the plurality of pieces of standard circuit block information so that each of the plurality of pieces of standard circuit block information satisfies the ideal clock signal condition and at least either of the first and second ideal assertion period conditions. Furthermore, the output function causes the computer to furnish the modified circuit information including a combination of the plurality of pieces of modified standard circuit block information. The timing design function can cause the computer to modify one piece of standard circuit block information associated with one circuit block located between either a tristate buffer on which the first ideal assertion period condition is imposed or a sequential circuit on which the second ideal assertion period condition is imposed and another sequential circuit located upstream from either the tristate buffer or the former sequential circuit for furnishing a control signal to either the tristate buffer or the former sequential circuit in response to the clock signal so that the piece of standard circuit block information satisfies a maximum delay time condition defining a maximum value of a time delay to be provided to the control signal with respect to the clock signal.
In accordance with another preferred embodiment of the present invention, the timing design function causes the computer to generate the modified circuit information by modifying the standard circuit information so that the standard circuit information satisfies the ideal clock signal condition and the first and second ideal assertion period conditions. Preferably, the timing design function can divide the standard circuit information into a plurality of pieces of standard circuit block information that are associated with a plurality of standard circuit blocks, respectively, while defining as boundaries one or more sequential circuits on which the ideal clock signal condition is imposed, one or more tristate buffers on each of which the first ideal assertion period condition is imposed, and one or more other sequential circuits on each of which the second ideal assertion period condition is imposed, and then modifies each of the plurality of pieces of standard circuit block information so that each of the plurality of pieces of standard circuit block information satisfies the ideal clock signal condition and the first and second ideal assertion period conditions. Furthermore, the output function causes the computer to furnish the modified circuit information including a combination of the plurality of pieces of modified standard circuit block information. In addition, the timing design function can cause the computer to modify one piece of standard circuit block information associated with one circuit block located between a tristate buffer on which the first ideal assertion period condition is imposed and a sequential circuit located upstream from the tristate buffer for furnishing a control signal to the tristate buffer in response to the clock signal so that the piece of standard circuit block information satisfies a maximum delay time condition defining a maximum value of a time delay to be provided to the control signal with respect to the clock signal. The timing design means can also or alternatively cause the computer to modify one piece of standard circuit block information associated with one circuit block located between a sequential circuit on which the second ideal assertion period condition is imposed and another sequential circuit located upstream from the former sequential circuit for furnishing a control signal to the former sequential circuit in response to the clock signal so that the piece of standard circuit block information satisfies a maximum delay time condition defining a maximum value of a time delay to be provided to the control signal with respect to the clock signal.
In accordance with another aspect of the present invention, there is provided a computer-implemented logic synthesis method for generating information about a constitution of target circuitry on which a logic synthesis function is to be performed based on specifications of the target circuitry written in a hardware description language, the method comprising the steps of: generating standard circuit information about the target circuitry based on the specifications of the target circuitry, the standard circuit information logically matching the specifications; and modifying the standard circuit information so that the standard circuit information satisfies both an ideal clock signal condition defining an ideal clock signal to be applied to one or more sequential circuits included in the target circuitry, and at least either of a first ideal assertion period condition defining an ideal period of time during which each of one or more tristate buffers included in the target circuitry is asserted and a second ideal assertion period condition defining an ideal period of time during which each of one or more sequential circuits each for latching an output of a tristate buffer, which are included in the target circuitry is asserted.
The modifying step can include the steps of dividing the standard circuit information into a plurality of pieces of standard circuit block information that are associated with a plurality of standard circuit blocks, respectively, while defining as boundaries one or more sequential circuits on which the ideal clock signal condition is imposed, and at least either of one or more tristate buffers on each of which the first ideal assertion period condition is imposed and one or more other sequential circuits on each of which the second ideal assertion period condition is imposed; and modifying each of the plurality of pieces of standard circuit block information so that each of the plurality of pieces of standard circuit block information satisfies the ideal clock signal condition and at least either of the first and second ideal assertion period conditions. Furthermore, in the outputting step the modified circuit information including a combination of the plurality of pieces of modified standard circuit block information is furnished. In addition, the modifying step can include the step of modifying one piece of standard circuit block information associated with one circuit block located between a tristate buffer on which the first ideal assertion period condition is imposed or a sequential circuit on which the second ideal assertion period condition is imposed and another sequential circuit located upstream from either the tristate buffer or the former sequential circuit for furnishing a control signal to either the tristate buffer or the former sequential circuit in response to the clock signal so that the piece of standard circuit block information satisfies a maximum delay time condition defining a maximum value of a time delay to be provided to the control signal with respect to the clock signal.
In accordance with a preferred embodiment of the present invention, in the modifying step, the standard circuit information is modified so that the standard circuit information satisfies the ideal clock signal condition and the first and second ideal assertion period conditions. Preferably, the modifying step can include the steps of dividing the standard circuit information into a plurality of pieces of standard circuit block information that are associated with a plurality of standard circuit blocks, respectively, while defining as boundaries one or more sequential circuits on which the ideal clock signal condition is imposed, one or more tristate buffers on each of which the first ideal assertion period condition is imposed, and one or more other sequential circuits on each of which the second ideal assertion period condition is imposed; and modifying each of the plurality of pieces of standard circuit block information so that each of the plurality of pieces of standard circuit block information satisfies the ideal clock signal condition and the first and second ideal assertion period conditions. Furthermore, in the outputting step the modified circuit information including a combination of the plurality of pieces of modified standard circuit block information is furnished. The modifying step can include the step of modifying one piece of standard circuit block information associated with one circuit block located between a tristate buffer on which the first ideal assertion period condition is imposed and a sequential circuit located upstream from the tristate buffer for furnishing a control signal to the tristate buffer in response to the clock signal so that the piece of standard circuit block information satisfies a maximum delay time condition defining a maximum value of a time delay to be provided to the control signal with respect to the clock signal. The modifying step can also or alternatively include the step of modifying one piece of standard circuit block information associated with one circuit block located between a sequential circuit on which the second ideal assertion period condition is imposed and another sequential circuit located upstream from the former sequential circuit for furnishing a control signal to the former sequential circuit in response to the clock signal so that the piece of standard circuit block information satisfies a maximum delay time condition defining a maximum value of a time delay to be provided to the control signal with respect to the clock signal.
In accordance with another aspect of the present invention, there is provided a logic synthesis apparatus for generating information about a constitution of target circuitry based on specifications of the target circuitry written in a hardware description language, comprising: a storage unit for storing the specifications of the target circuitry, an ideal clock signal condition defining an ideal clock signal to be applied to one or more sequential circuits included in the target circuitry, and at least either of a first ideal assertion period condition defining an ideal period of time during which each of one or more tristate buffers included in the target circuitry is asserted and a second ideal assertion period condition defining an ideal period of time during which each of one or more other sequential circuits each for latching an output of a tristate buffer, which are included in the target circuitry is asserted; a standard design unit for generating standard circuit information about the target circuitry based on the specifications stored in the storage unit, the standard circuit information logically matching the specifications; a timing design unit for generating modified circuit information by modifying the standard circuit information so that the standard circuit information satisfies both the ideal clock signal condition and at least either of the first and second ideal assertion period conditions; and an output unit for outputting the modified circuit information.
Preferably, the timing design unit can divide the standard circuit information into a plurality of pieces of standard circuit block information that are associated with a plurality of standard circuit blocks, respectively, while defining as boundaries one or more sequential circuits on which the ideal clock signal condition is imposed, and at least either of one or more tristate buffers on each of which the first ideal assertion period condition is imposed and one or more other sequential circuits on each of which the second ideal assertion period condition is imposed, and then modifies each of the plurality of pieces of standard circuit block information so that each of the plurality of pieces of standard circuit block information satisfies both the ideal clock signal condition and at least either of the first and second ideal assertion period conditions. Furthermore, the output unit furnishes the modified circuit information including a combination of the plurality of pieces of modified standard circuit block information. In addition, the timing design unit can modify one piece of standard circuit block information associated with one circuit block located between a tristate buffer on which the first ideal assertion period condition is imposed or a sequential circuit on which the second ideal assertion period condition is imposed and another sequential circuit located upstream from the former sequential circuit for furnishing a control signal to the former sequential circuit in response to the clock signal so that the piece of standard circuit block information satisfies a maximum delay time condition defining a maximum value of a time delay to be provided to the control signal with respect to the clock signal.
In accordance with a preferred embodiment of the present invention, the timing design unit modifies the standard circuit information so that the standard circuit information satisfies the ideal clock signal condition and the first and second ideal assertion period conditions. The timing design unit can divide the standard circuit information into a plurality of pieces of standard circuit block information that are associated with a plurality of standard circuit blocks, respectively, while defining as boundaries one or more sequential circuits on which the ideal clock signal condition is imposed, one or more tristate buffers on each of which the first ideal assertion period condition is imposed, and one or more other sequential circuits on each of which the second ideal assertion period condition is imposed, and then modifies each of the plurality of pieces of standard circuit block information so that each of the plurality of pieces of standard circuit block information satisfies the ideal clock signal condition and the first and second ideal assertion period conditions. Furthermore, the output unit furnishes the modified circuit information including a combination of the plurality of pieces of modified standard circuit block information. In addition, the timing design unit can modify one piece of standard circuit block information associated with one circuit block located between a tristate buffer on which the first ideal assertion period condition is imposed and a sequential circuit located upstream from the tristate buffer for furnishing a control signal to the tristate buffer in response to the clock signal so that the piece of standard circuit information satisfies a maximum delay time condition defining a maximum value of a time delay to be provided to the control signal with respect to the clock signal, and one piece of standard circuit block information associated with one circuit block located between a sequential circuit on which the second ideal assertion period condition is imposed and another sequential circuit located upstream from the former sequential circuit for furnishing a control signal to the former sequential circuit in response to the clock signal so that the piece of standard circuit information satisfies a maximum delay time condition defining a maximum value of a time delay to be provided to the control signal with respect to the clock signal.